37 lines
872 B
Systemverilog
37 lines
872 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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int i;
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string value;
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function automatic int count();
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++i;
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value = {value, $sformatf(" count%0d", i)};
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return i;
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endfunction
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initial begin
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value = "";
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i = 0;
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while (count() <= 2) begin
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// verilator unroll_disable
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value = {value, " loop"};
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end
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`checks(value, " count1 loop count2 loop count3");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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