47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int a, b;
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int pos;
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function string value;
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// Debug 'initial' loops first
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value = "";
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for (int exit_a = 0; exit_a < 2; ++exit_a) begin
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for (int exit_b = 0; exit_b < 3; ++exit_b) begin
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b = 0;
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value = {value, $sformatf("exit_a %0d %0d", exit_a, exit_b)};
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for (a = 0; a < 3; ++a) begin : a_loop
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value = {value, $sformatf(" A%0d", a * 10 + b)};
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for (b = 0; b < 3; ++b) begin : b_loop
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value = {value, $sformatf(" B%0d", a * 10 + b)};
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if (exit_b == 1 && b == 1) disable b_loop;
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value = {value, $sformatf(" C%0d", a * 10 + b)};
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if (exit_b == 2 && a == 1) disable a_loop;
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value = {value, $sformatf(" D%0d", a * 10 + b)};
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end
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value = {value, $sformatf(" Y%0d", a * 10 + b)};
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if (exit_a == 1 && a == 1) disable a_loop;
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value = {value, $sformatf(" Z%0d", a * 10 + b)};
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end
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value = {value, "\n"};
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end
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end
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endfunction
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localparam string VALUE = value();
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initial begin
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$write("%s", VALUE);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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