55 lines
1.3 KiB
Systemverilog
55 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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class Cls;
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int m_index;
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function automatic int get_index();
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int rtn;
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rtn = m_index;
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++m_index;
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`ifdef VERILATOR
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return $c(rtn); // Avoid optimizations
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`else
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return rtn;
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`endif
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endfunction
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endclass
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module t (/*AUTOARG*/);
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Cls cls;
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int array[10];
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initial begin
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cls = new;
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// Common UVM construct 'id_cnt[get_id()]++;'
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// Properly avoid/handle SIDEEFF warnings
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cls.m_index = 5;
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array[5] = 50;
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array[6] = 60;
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array[7] = 70;
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array[8] = 80;
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array[cls.get_index()]++;
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`checkd(array[5], 51);
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array[cls.get_index()]++;
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`checkd(array[6], 61);
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++array[cls.get_index()];
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`checkd(array[7], 71);
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++array[cls.get_index()];
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`checkd(array[8], 81);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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