34 lines
923 B
Systemverilog
34 lines
923 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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localparam TEN = 10;
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localparam string PCTPCT = "%%";
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if (0) begin
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$info;
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$info("User elaboration-time info");
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$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
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$warning;
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$warning("User elaboration-time warning");
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$warning(1); // Check can convert arguments to format
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$error("User elaboration-time error");
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end
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initial begin
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$info;
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$info("User run-time info");
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$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
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$warning;
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$warning("User run-time warning");
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$warning(1); // Check can convert arguments to format
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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