45 lines
1.2 KiB
Systemverilog
45 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class X;
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typedef enum int {
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INITIAL, RUNNING, SUSPENDED, COMPLETING, DONE
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} state_t;
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static string state_names[state_t] = '{
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INITIAL: "INITIAL",
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RUNNING: "RUNNING",
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SUSPENDED: "SUSPENDED",
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COMPLETING: "COMPLETING",
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DONE: "DONE"
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};
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protected state_t state;
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function new();
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this.state = INITIAL;
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`checks(state_names[this.state], "INITIAL");
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this.state = RUNNING;
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`checks(state_names[this.state], "RUNNING");
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endfunction
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endclass
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module t;/*AUTOARG*/
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initial begin
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X x = new;
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$finish;
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end
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endmodule
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