13 lines
876 B
Plaintext
13 lines
876 B
Plaintext
%Error: t/t_bigmem_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
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: ... note: In instance 't_bigmem'
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14 | if (wen) mem[addr] <= data;
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Warning-WIDTHTRUNC: t/t_bigmem_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits.
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: ... note: In instance 't_bigmem'
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14 | if (wen) mem[addr] <= data;
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| ^~
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... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
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... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
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%Error: Exiting due to
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