30 lines
715 B
Systemverilog
30 lines
715 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam int width = 8;
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typedef logic [width-1:0] [15:0] two_dee_t;
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typedef logic[$clog2(width)-1:0] index_t;
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two_dee_t the_two_dee;
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initial begin
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the_two_dee[index_t'(5)][7:0] = 8'hab;
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the_two_dee[index_t'(5)][15:8] = 8'h12;
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end
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always @ (posedge clk) begin
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if (the_two_dee[5] != 16'h12ab) $stop();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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