39 lines
1.1 KiB
Systemverilog
39 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(aw_addr, orig_aw_size);
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typedef logic [63:0] addr_t;
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typedef logic [7:0][7:0] mst_data_t;
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logic [127:0] slv_req_i_w_data;
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input addr_t aw_addr;
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mst_data_t w_data;
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input logic [2:0] orig_aw_size;
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always_comb begin
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// verilator lint_off WIDTHEXPAND
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automatic addr_t mst_port_offset = aw_addr[2:0];
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automatic addr_t slv_port_offset = aw_addr[3:0];
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w_data = '0;
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for (int b=0; b<16; b++) begin
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if ((b >= slv_port_offset) &&
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(b - slv_port_offset < (1 << orig_aw_size)) &&
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(b + mst_port_offset - slv_port_offset < 8)) begin
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automatic addr_t index = b + mst_port_offset - slv_port_offset;
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// verilator lint_on WIDTHEXPAND
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// [#][7:0] = [ +: 8]
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w_data[index] = slv_req_i_w_data[8*b +: 8];
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end
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end
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end
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endmodule
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