34 lines
918 B
Systemverilog
34 lines
918 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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typedef enum {
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UVM_TLM_READ_COMMAND,
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UVM_TLM_WRITE_COMMAND,
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UVM_TLM_IGNORE_COMMAND
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} uvm_tlm_command_e;
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module t(/*AUTOARG*/);
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initial begin
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bit array[] = new [8];
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int unsigned m_length;
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uvm_tlm_command_e m_command;
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m_length = 2;
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array = '{0, 0, 0, 0, 0, 0, 1, 0};
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array = new [$bits(m_length)] (array);
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m_command = uvm_tlm_command_e'({ << bit { array }});
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`checkh(m_command, 'h40)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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