33 lines
623 B
Systemverilog
33 lines
623 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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class A;
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int num;
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function new(int num);
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this.num = num;
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endfunction
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endclass
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class B;
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static A obj = new(2);
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endclass
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class C;
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static A obj = new(5);
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endclass
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initial begin
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#1;
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$display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj));
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if (B::obj == C::obj) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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