45 lines
1020 B
Systemverilog
45 lines
1020 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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class Base;
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int m_s = 2;
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function new(int def = 3);
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m_s = def;
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endfunction
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endclass
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class Cls5Exp extends Base(5);
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int m_a = 11;
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function new(int def = 42); // Explicit new
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m_a = def;
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endfunction
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endclass
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class Cls5Imp extends Base(5);
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int m_a = 12;
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// Implicit new
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endclass
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module t ();
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Cls5Exp ce;
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Cls5Imp ci;
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initial begin
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ce = new(37);
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`checkh(ce.m_s, 5);
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`checkh(ce.m_a, 37);
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ci = new;
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`checkh(ci.m_s, 5);
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`checkh(ci.m_a, 12);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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