80 lines
1.8 KiB
Systemverilog
80 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Base;
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class BaseInner;
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int value = 10;
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function void test;
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if (value != 10) $stop;
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if (this.value != 10) $stop;
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value = 20;
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if (value != 20) $stop;
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this.value = 30;
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if (value != 30) $stop;
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endfunction
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endclass
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int value = 1;
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BaseInner inner = new;
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function void test;
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if (value != 1) $stop;
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if (this.value != 1) $stop;
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value = 2;
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if (value != 2) $stop;
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this.value = 3;
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if (value != 3) $stop;
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endfunction
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endclass
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class Cls extends Base;
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class BaseInner extends Base::BaseInner;
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int value = 100;
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function void test;
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if (value != 100) $stop;
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if (this.value != 100) $stop;
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if (super.value != 10) $stop;
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super.test();
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if (value != 100) $stop;
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if (this.value != 100) $stop;
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if (super.value != 30) $stop;
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value = 200;
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if (value != 200) $stop;
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this.value = 300;
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if (value != 300) $stop;
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endfunction
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endclass
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int value = 20;
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BaseInner inner = new;
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function void test;
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if (value != 20) $stop;
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if (this.value != 20) $stop;
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if (super.value != 1) $stop;
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super.test();
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if (this.value != 20) $stop;
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super.value = 9;
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this.value = 29;
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if (super.value != 9) $stop;
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if (value != 29) $stop;
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inner.test();
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.test();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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