42 lines
898 B
Systemverilog
42 lines
898 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Base;
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class Inner;
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int value = 10;
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function void testBaseInner;
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if (value != 10) $stop;
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endfunction
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endclass
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int value = 1;
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Inner inner = new;
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function void testBase;
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if (value != 1) $stop;
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if (inner.value != 10) $stop;
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endfunction
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endclass
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class Cls extends Base;
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function void testDerived;
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if (value != 1) $stop;
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if (inner.value != 10) $stop;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.testBase();
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c.testDerived();
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c.inner.testBaseInner();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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