77 lines
1.6 KiB
Systemverilog
77 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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function int fi();
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return 10;
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endfunction
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function void fv();
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endfunction
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task t();
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endtask
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static function int sfi();
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return 10;
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endfunction
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static function void sfv();
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endfunction
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static task st();
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endtask
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endclass
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module t (/*AUTOARG*/);
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function int mod_fi();
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return 10;
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endfunction
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function void mod_fv();
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endfunction
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task mod_t();
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endtask
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initial begin
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Cls c;
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c = new;
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// For test of calling function in void context, see t_func_void_bad.v
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// Module
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if (mod_fi() != 10) $stop; // OK
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void'(mod_fi()); // OK
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mod_fv(); // Warn IGNOREDRETURN
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void'(mod_fv()); // OK
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if (mod_fv() == 10) $stop; // Bad call of task as function
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mod_t(); // OK
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if (mod_t() == 10) $stop; // Bad call of task as function
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// Member functions
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if (c.fi() != 10) $stop; // OK
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void'(c.fi()); // OK
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c.fv(); // Ok
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void'(c.fv()); // OK
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if (c.fv() == 10) $stop; // Bad
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c.t(); // OK
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if (c.t() == 10) $stop; // Bad
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// Static member functions
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if (c.sfi() != 10) $stop; // OK
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void'(c.sfi()); // OK
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c.sfv(); // Ok
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void'(c.sfv()); // OK
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if (c.sfv() == 10) $stop; // Bad
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c.st(); // OK
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if (c.st() == 10) $stop; // Bad
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$stop;
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end
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endmodule
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