91 lines
1.9 KiB
Systemverilog
91 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class NodeList;
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class Node;
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string name;
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Node link;
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function new();
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name = "node";
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endfunction
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endclass
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Node head;
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endclass
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class NodeTree;
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class Node;
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int id;
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Node link;
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endclass
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Node root;
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endclass
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// Based on IEEE 1800-2017 section 8.23 Nested classes
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class Outer;
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int outerProp;
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local int outerLocalProp;
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static int outerStaticProp;
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static local int outerLocalStaticProp;
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class Inner;
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function void innerMethod(Outer h);
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outerStaticProp = 1;
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outerLocalStaticProp = 1;
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h.outerProp = 1;
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h.outerLocalProp = 1;
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endfunction
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endclass
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endclass
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module t(/*AUTOARG*/);
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initial begin
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NodeList n = new;
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NodeList::Node n1 = new;
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NodeList::Node n2 = new;
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NodeTree tr = new;
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NodeTree::Node t1 = new;
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NodeTree::Node t2 = new;
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Outer o = new;
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Outer::Inner i = new;
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i.innerMethod(o);
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if(o.outerProp != 1) $stop;
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if(Outer::outerStaticProp != 1) $stop;
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if (n1.name != "node") $stop;
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n1.name = "n1";
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if (n1.name != "n1") $stop;
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n2.name = "n2";
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if (n2.name != "n2") $stop;
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n.head = n1;
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n1.link = n2;
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if (n.head.name != "n1") $stop;
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if (n.head.link.name != "n2") $stop;
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t1.id = 1;
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if (t1.id != 1) $stop;
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t2.id = 2;
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if (t2.id != 2) $stop;
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tr.root = t1;
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t1.link = t2;
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if (tr.root.id != 1) $stop;
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if (tr.root.link.id != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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