67 lines
1.4 KiB
Systemverilog
67 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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class Base;
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int m_ia = 10;
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function new(int i);
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m_ia = i;
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endfunction
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endclass
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class ClsNoArg extends Base;
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function new();
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super.new(5);
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endfunction : new
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endclass
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class ClsArg extends Base;
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function new(int i, int j);
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super.new(i + j);
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endfunction
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endclass
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class ClsParam #(int ADD = 100) extends Base;
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function new(int def = 42);
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super.new(def + ADD);
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Base b;
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ClsNoArg c1;
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ClsArg c2;
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ClsParam#(100) c3;
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ClsParam#(200) c4;
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c1 = new;
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`checkd(c1.m_ia, 5);
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b = ClsNoArg::new;
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`checkd(b.m_ia, 5);
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c2 = new(20, 1);
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`checkd(c2.m_ia, 21);
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b = ClsArg::new(20, 1);
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`checkd(b.m_ia, 21);
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c3 = new(33);
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`checkd(c3.m_ia, 133);
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b = ClsParam#(100)::new(33);
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`checkd(b.m_ia, 133);
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c4 = new(44);
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`checkd(c4.m_ia, 244);
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b = ClsParam#(200)::new(44);
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`checkd(b.m_ia, 244);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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