42 lines
888 B
Systemverilog
42 lines
888 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package my_pkg;
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typedef enum logic [1:0] {
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SIG_0, SIG_1, SIG_2
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} sig_t;
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endpackage : my_pkg
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module t;
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import my_pkg::*;
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typedef logic [7:0] foo_t;
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typedef logic [31:0] bar_t;
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bar_t [1:0] the_bars;
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foo_t [0:0][1:0] the_foos;
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always_comb begin
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the_bars = {32'd7, 32'd8};
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the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])};
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end
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logic [6:0] data;
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logic [2:0] opt;
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assign data = 7'b110_0101;
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assign opt = {data[5], sig_t'(data[1:0])};
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initial begin
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if (the_foos != 'h0708) $stop();
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if (opt != 'b101) $stop();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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