28 lines
580 B
Systemverilog
28 lines
580 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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int global_variable = 0;
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function int side_effect;
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global_variable++;
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return 1;
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endfunction
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module t (/*AUTOARG*/);
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reg [15:0] x;
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reg [15:0] y;
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initial begin
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{x, y} = side_effect() + 2;
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if (y != 3) $stop;
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if (x != 0) $stop;
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if (global_variable != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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