verilator/test_regress/t/t_config_include_bad.out

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%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
7 | include "meant_to_tick_include.v"
| ^~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_config_include_bad.v:7:9: syntax error, unexpected STRING
7 | include "meant_to_tick_include.v"
| ^~~~~~~~~~~~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to