19 lines
446 B
Verilog
19 lines
446 B
Verilog
// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// lib.map file:
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include ./t_config_libmap_inc.map
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library rtllib *.v;
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library rtllib2 *.v, *.sv;
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library rtllib3 *.v -incdir *.vh;
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library rtllib4 *.v -incdir *.vh, *.svh;
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config cfg;
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design t;
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endconfig
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