31 lines
746 B
Systemverilog
31 lines
746 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module m1;
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parameter string P1 = "p1.unchanged";
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parameter string P2 = "p2.unchanged";
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initial $display("m1 %%m=%m %%l=%l P1=%s P2=%s", P1, P2);
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endmodule
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module t;
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m1 u_1a();
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m1 u_1b();
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m1 u_1c();
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final $write("*-* All Finished *-*\n");
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endmodule
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config cfg1;
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localparam P1 = "cfg.p1";
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localparam P2 = "cfg.p2";
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design t;
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instance t.u_1a use #(.P1(), .P2("override.u_a.p2"));
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instance t.u_1b use #(); // All parameters back to default
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instance t.u_1c use #(.P1(P1), .P2(P2));
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endconfig
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