50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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m10 u_10();
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m20 u_20();
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m21 u_21();
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m22 u_22();
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m23 u_23();
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m24 u_24();
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m30 u_30();
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m31 u_31();
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m32 u_32();
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m40 u_40();
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m41 u_41();
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m42 u_42();
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m43 u_43();
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final $write("*-* All Finished *-*\n");
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endmodule
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config cfg;
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design t;
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// Test uses m10
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default liblist; // Ignored
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default liblist liba libb;
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// Test uses m20-29
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instance t.m20 liblist; // Use parent's cell library
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instance t.m21 liblist libc;
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instance t.m22 liblist libc libd; // m22 in libc
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instance t.m23 liblist libc libd; // m23 in libd
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instance t.m24 liblist libc libd; // m24 in default (libb)
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// Test uses m30-39
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instance t.m30 use cell_identifier;
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instance t.m31 use lib_id.cell_id;
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instance t.m32 use #();
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// Test uses m40-49
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cell m40 liblist libc libd;
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cell work.m41 liblist libc libd;
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cell m42 use m42alt;
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cell work.m43 use work.m43alt;
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endconfig
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