116 lines
3.0 KiB
Systemverilog
Executable File
116 lines
3.0 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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class AssocIntegralWide;
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rand bit [31:0] assoc_array[bit[64:0]];
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rand bit [31:0] assoc_array_128[bit[128:0]];
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rand bit [31:0] assoc_array_2d[bit[64:0]][bit[128:0]];
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constraint valid_entries {
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assoc_array[65'd6] == 32'd8;
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assoc_array[65'h1FFFFFFFFFFFFFFFF] == 32'hDEADBEEF;
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assoc_array_128[129'd6] == 32'd16;
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assoc_array_128[129'h1FFFFFFFFFFFFFFFFFFFFFFFF] == 32'hCAFEBABE;
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assoc_array_2d[65'd6][129'd6] == 32'd32;
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assoc_array_2d[65'h1FFFFFFFFFFFFFFFF][129'h1FFFFFFFFFFFFFFFFFFFFFFFF] == 32'hBADF00D;
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}
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// Constructor to initialize arrays
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function new();
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assoc_array[65'd0] = 32'd0;
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assoc_array[65'd6] = 32'd0;
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assoc_array[65'h1FFFFFFFFFFFFFFFF] = 32'd0;
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assoc_array_128[129'd0] = 32'd0;
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assoc_array_128[129'd6] = 32'd0;
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assoc_array_128[129'h1FFFFFFFFFFFFFFFFFFFFFFFF] = 32'd0;
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assoc_array_2d[65'd6][129'd6] = 32'd0;
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assoc_array_2d[65'h1FFFFFFFFFFFFFFFF][129'h1FFFFFFFFFFFFFFFFFFFFFFFF] = 32'd0;
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endfunction
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// Self-check function to verify constraints
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function void self_check();
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if (assoc_array[65'd6] != 32'd8)
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$stop;
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if (assoc_array[65'h1FFFFFFFFFFFFFFFF] != 32'hDEADBEEF)
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$stop;
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if (assoc_array_128[129'd6] != 32'd16)
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$stop;
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if (assoc_array_128[129'h1FFFFFFFFFFFFFFFFFFFFFFFF] != 32'hCAFEBABE)
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$stop;
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if (assoc_array_2d[65'd6][129'd6] != 32'd32)
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$stop;
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if (assoc_array_2d[65'h1FFFFFFFFFFFFFFFF][129'h1FFFFFFFFFFFFFFFFFFFFFFFF] != 32'hBADF00D)
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$stop;
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endfunction
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endclass
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class AssocStringWide;
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rand bit [31:0] array_32[string];
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rand bit [31:0] array_64[string];
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rand bit [31:0] array_96[string];
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rand bit [31:0] array_128[string];
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constraint valid_entries {
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// <= 32 bits
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array_32["pv"] == 32'd10;
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// > 32 and <= 64 bits
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array_64["verilog"] == 32'd20;
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// > 32 and <= 64 bits
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array_96["verilator"] == 32'd30;
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// > 64 and <= 96 bits
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array_128["systemverilog"] == 32'd40;
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}
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function new();
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array_32["pv"] = 32'd0;
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array_64["verilog"] = 32'd0;
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array_96["verilator"] = 32'd0;
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array_128["systemverilog"] = 32'd0;
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endfunction
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function void self_check();
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if (array_32["pv"] != 32'd10) $stop;
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if (array_64["verilog"] != 32'd20) $stop;
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if (array_96["verilator"] != 32'd30) $stop;
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if (array_128["systemverilog"] != 32'd40) $stop;
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endfunction
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endclass
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module t_constraint_assoc_arr_wide;
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AssocIntegralWide integral_wide;
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AssocStringWide string_wide;
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int success;
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initial begin
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integral_wide = new();
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string_wide = new();
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success = integral_wide.randomize();
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if (success != 1) $stop;
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integral_wide.self_check();
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success = string_wide.randomize();
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if (success != 1) $stop;
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string_wide.self_check();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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