78 lines
1.5 KiB
Systemverilog
78 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, cond) \
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begin \
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longint prev_result; \
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int ok = 0; \
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if (!bit'(cl.randomize())) $stop; \
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prev_result = longint'(field); \
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if (!(cond)) $stop; \
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repeat(9) begin \
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longint result; \
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if (!bit'(cl.randomize())) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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class Foo;
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int x;
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endclass
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class Bar;
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rand int y;
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endclass
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class Packet;
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rand int rf;
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int state;
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rand int a;
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rand Foo foo;
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Bar bar;
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constraint c1 { rf == state; }
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constraint c2 { a > foo.x; a < bar.y; }
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function new(int s, int x, int y);
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state = s;
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foo = new;
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foo.x = x;
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bar = new;
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bar.y = y;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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Packet p;
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int v;
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initial begin
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p = new(123, 10, 20);
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v = p.randomize();
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if (v != 1) $stop;
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if (p.rf != 123) $stop;
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`check_rand(p, p.a, p.a > 10 && p.a < 20)
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if (p.foo.x != 10) $stop;
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if (p.bar.y != 20) $stop;
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p.state = 234;
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v = p.randomize();
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if (v != 1) $stop;
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if (p.rf != 234) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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