364 lines
8.3 KiB
Systemverilog
364 lines
8.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg toggle;
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initial toggle=0;
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integer cyc;
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initial cyc=1;
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wire [7:0] cyc_copy = cyc[7:0];
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alpha a1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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alpha a2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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beta b1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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beta b2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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tsk t1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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off o1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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tab tab1 (/*AUTOINST*/
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// Inputs
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.clk (clk));
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par par1 (/*AUTOINST*/);
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cond cond1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.cyc (cyc));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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toggle <= '0;
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// Single and multiline if
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if (cyc==3) $write("");
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if (cyc==3)
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begin
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$write("");
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end
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// Single and multiline else
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if (cyc==3) ; else $write("");
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if (cyc==3) ;
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else
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begin
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$write("");
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end
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// Single and multiline if else
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if (cyc==3) $write(""); else $write("");
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if (cyc==3)
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begin
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$write("");
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end
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else
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begin
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$write("");
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end
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// multiline elseif
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if (cyc==3)
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begin
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$write("");
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end
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else if (cyc==4)
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begin
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$write("");
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end
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else if (cyc==5)
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begin
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$write("");
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end
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else
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begin
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$write("");
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end
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// Single and multiline while
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while (0);
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while (0) begin
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$write("");
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end
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do ; while (0);
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do begin
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$write("");
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end while (0);
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//===
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// Task and complicated
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if (cyc==3) begin
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toggle <= '1;
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end
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else if (cyc==5) begin
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`ifdef VERILATOR
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$c("this->call_task();");
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`else
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call_task();
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`endif
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end
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else if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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task call_task;
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/* verilator public */
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t1.center_task(1'b1);
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endtask
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endmodule
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module alpha (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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always @ (posedge clk) begin
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if (toggle) begin // CHECK_COVER(0,"top.t.a*",18)
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$write("");
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// t.a1 and t.a2 collapse to a count of 2
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end
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if (toggle) begin // *** t_cover_line.vlt turns this off
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$write(""); // CHECK_COVER_MISSING(0)
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// This doesn't even get added
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`ifdef ATTRIBUTE
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// verilator coverage_block_off
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`endif
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end
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end
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endmodule
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module beta (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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/* verilator public_module */
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always @ (posedge clk) begin
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$write(""); // Always covered
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if (0) begin // CHECK_COVER(0,"top.t.b*",0)
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// Make sure that we don't optimize away zero buckets
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$write("");
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end
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if (toggle) begin // CHECK_COVER(0,"top.t.b*",2)
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// t.b1 and t.b2 collapse to a count of 2
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$write("");
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end
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if (toggle) begin : block
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// This doesn't
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`ifdef ATTRIBUTE
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// verilator coverage_block_off
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`endif
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begin end // *** t_cover_line.vlt turns this off (so need begin/end)
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if (1) begin end // CHECK_COVER_MISSING(0)
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$write(""); // CHECK_COVER_MISSING(0)
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end
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end
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endmodule
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class Cls;
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bit m_toggle;
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function new(bit toggle);
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m_toggle = toggle;
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if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1)
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$write("");
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end
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endfunction
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static function void fstatic(bit toggle);
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if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1)
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$write("");
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end
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endfunction
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function void fauto();
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if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11)
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$write("");
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end
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endfunction
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endclass
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module tsk (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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/* verilator public_module */
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always @ (posedge clk) begin
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center_task(1'b0);
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end
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task center_task;
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input external;
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begin
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if (toggle) begin // CHECK_COVER(0,"top.t.t1",1)
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$write("");
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end
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if (external) begin // CHECK_COVER(0,"top.t.t1",1)
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$write("[%0t] Got external pulse\n", $time);
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end
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end
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begin
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Cls c = new(1'b1);
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c.fauto();
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Cls::fstatic(1'b1);
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end
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endtask
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endmodule
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module off (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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// verilator coverage_off
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always @ (posedge clk) begin
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if (toggle) begin
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$write(""); // CHECK_COVER_MISSING(0)
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// because under coverage_module_off
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end
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end
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// verilator coverage_on
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always @ (posedge clk) begin
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if (toggle) begin
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// because under coverage_module_off
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$write("");
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if (0) ; // CHECK_COVER(0,"top.t.o1",1)
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end
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end
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endmodule
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module tab (input clk);
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bit [3:0] cyc4;
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int decoded;
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always @ (posedge clk) begin
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case (cyc4)
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1: decoded = 10;
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2: decoded = 20;
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3: decoded = 30;
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4: decoded = 40;
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5: decoded = 50;
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default: decoded = 0;
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endcase
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end
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always @ (posedge clk) begin
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cyc4 <= cyc4 + 1;
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end
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endmodule
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module par();
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localparam int CALLS_FUNC = param_func(1);
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// We don't currently count elaboration time use towards coverage. This
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// seems safer for functions used both at elaboration time and not - but may
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// revisit this.
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function automatic int param_func(int i);
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if (i == 0) begin
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i = 99; // Uncovered
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end
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else begin
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i = i + 1;
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end
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return i;
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endfunction
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endmodule
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package my_pkg;
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int x = 1 ? 1 : 0;
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endpackage
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class Getter1;
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function int get_1;
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return 1;
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endfunction
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endclass
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module cond(input logic clk, input int cyc);
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logic a, b, c, d, e, f, g, h, k, l, m;
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logic [5:0] tab;
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typedef logic [7:0] arr_t[1:0];
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arr_t data[1:0];
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Getter1 getter1 = new;
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string s;
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function logic func_side_effect;
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$display("SIDE EFFECT");
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return 1;
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endfunction
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function arr_t get_arr;
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arr_t arr;
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return arr;
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endfunction
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assign a = (cyc == 0) ? clk : 1'bz;
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assign b = (cyc == 1) ? clk : 0;
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assign c = func_side_effect() ? clk : 0;
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always @(posedge clk) begin
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d = (cyc % 3 == 0) ? 1 : 0;
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s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]);
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end
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assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1;
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// ternary operator in condition shouldn't be included to the coverae
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assign f = (cyc != 0 ? 1 : 0) ? 1 : 0;
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// the same as in index
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assign tab[clk ? 1 : 0] = 1;
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assign m = tab[clk ? 3 : 4];
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for (genvar i = 0; i < 2; i++) begin
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assign g = clk ? 1 : 0;
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end
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always begin
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if (cyc == 5) h = cyc > 5 ? 1 : 0;
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else h = 1;
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data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr();
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// ternary operator in conditions should be skipped
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for (int i = 0; (i < 5) ? 1 : 0; i++) begin
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k = 1'(i);
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end
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for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin
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k = 1'(i);
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end
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if (k ? 1 : 0) k = 1;
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else k = 0;
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end
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endmodule
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