95 lines
3.3 KiB
Plaintext
95 lines
3.3 KiB
Plaintext
// // verilator_coverage annotation
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface intf();
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logic foo;
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logic [31:0] bar;
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logic [127:0] baz;
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc;
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%000001 initial cyc=1;
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-000001 point: comment=block hier=top.t
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intf intfs [2] ();
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intf intf_sel_ff();
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intf intf_sel_comb();
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intf intf_sel_assign();
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%000001 always_comb begin
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-000001 point: comment=block hier=top.t
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%000001 intfs[0].bar = 123;
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-000001 point: comment=block hier=top.t
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%000001 intfs[1].bar = 456;
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-000001 point: comment=block hier=top.t
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end
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%000009 always_ff @ (posedge clk) begin
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-000009 point: comment=block hier=top.t
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%000009 {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <=
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-000009 point: comment=block hier=top.t
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%000009 cyc[0] ?
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-000009 point: comment=cond_then hier=top.t
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-000009 point: comment=cond_else hier=top.t
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%000009 {intfs[1].foo, intfs[1].bar, intfs[1].baz} :
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-000009 point: comment=cond_then hier=top.t
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%000009 {intfs[0].foo, intfs[0].bar, intfs[0].baz};
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-000009 point: comment=cond_else hier=top.t
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end
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000010 always_comb begin
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+000010 point: comment=block hier=top.t
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000010 {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} =
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+000010 point: comment=block hier=top.t
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000010 cyc[0] ?
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+000010 point: comment=cond_then hier=top.t
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+000010 point: comment=cond_else hier=top.t
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000010 {intfs[1].foo, intfs[1].bar, intfs[1].baz} :
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+000010 point: comment=cond_then hier=top.t
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000010 {intfs[0].foo, intfs[0].bar, intfs[0].baz};
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+000010 point: comment=cond_else hier=top.t
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end
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assign
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{intf_sel_assign.foo, intf_sel_assign.bar, intf_sel_assign.baz} =
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000010 cyc[0] ?
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+000010 point: comment=cond_then hier=top.t
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+000010 point: comment=cond_else hier=top.t
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000010 {intfs[1].foo, intfs[1].bar, intfs[1].baz} :
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+000010 point: comment=cond_then hier=top.t
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000010 {intfs[0].foo, intfs[0].bar, intfs[0].baz};
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+000010 point: comment=cond_else hier=top.t
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%000009 always @ (posedge clk) begin
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-000009 point: comment=block hier=top.t
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%000009 cyc <= cyc + 1;
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-000009 point: comment=block hier=top.t
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%000008 if (cyc==9) begin
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-000008 point: comment=else hier=top.t
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-000001 point: comment=if hier=top.t
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%000001 if (intf_sel_ff.bar != 123) $stop();
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-000001 point: comment=else hier=top.t
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%000001 if (intf_sel_comb.bar != 456) $stop();
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-000001 point: comment=else hier=top.t
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%000001 if (intf_sel_assign.bar != 456) $stop();
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-000001 point: comment=else hier=top.t
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%000001 $write("*-* All Finished *-*\n");
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-000001 point: comment=if hier=top.t
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%000001 $finish;
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-000001 point: comment=if hier=top.t
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end
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end
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endmodule
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