verilator/test_regress/t/t_cover_sva_trace.out

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$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$scope module t $end
$var wire 1 # clk $end
$var wire 1 $ toggle $end
$var wire 32 % cyc [31:0] $end
$scope module suba $end
$var wire 1 # clk $end
$var wire 1 $ toggle $end
$var wire 32 & cyc [31:0] $end
$var wire 32 ' cyc_eq_5_vlCoverageUserTrace [31:0] $end
$upscope $end
$scope module subb $end
$var wire 1 # clk $end
$var wire 1 $ toggle $end
$var wire 32 & cyc [31:0] $end
$var wire 32 ( cyc_eq_5_vlCoverageUserTrace [31:0] $end
$upscope $end
$scope module subc $end
$var wire 1 # clk $end
$var wire 1 $ toggle $end
$var wire 32 & cyc [31:0] $end
$var wire 32 ) cyc_eq_5_vlCoverageUserTrace [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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