36 lines
708 B
Systemverilog
36 lines
708 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// See bug5821
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`define STRINGIFY(x) `"x`"
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module imply(input logic p, input logic q, output logic r);
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always_comb begin
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r = p | q;
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end
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endmodule
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module t();
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logic p;
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logic q;
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logic r;
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imply dut(.p(p), .q(q), .r(r));
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initial begin
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars();
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//
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p = 1;
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q = 0;
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$strobe("[%0t] %d, %d, %d", $time, p, q, r);
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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