20 lines
469 B
Systemverilog
20 lines
469 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off COVERIGN */
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module t;
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covergroup cgArgs(int var1, int var2=42);
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endgroup
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cgArgs cov1 = new(69, 77);
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cgArgs cov2 = new(69);
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function x();
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cov1.sample();
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cov2.get_coverage();
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endfunction;
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endmodule
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