40 lines
1.2 KiB
Systemverilog
40 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off COVERIGN */
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module t;
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class base;
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function new();
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g1 = new(0);
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endfunction
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enum {red, green, blue} color;
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covergroup g1 (bit [3:0] a) with function sample(bit b);
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option.weight = 10;
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option.per_instance = 1;
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coverpoint a;
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coverpoint b;
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c: coverpoint color;
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endgroup
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endclass
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class derived extends base;
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bit d;
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function new();
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super.new();
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endfunction
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covergroup extends g1;
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option.weight = 1; // overrides the weight from base g1
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// uses per_instance = 1 from base g1
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c: coverpoint color // overrides the c coverpoint in base g1
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{
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ignore_bins ignore = {blue};
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}
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coverpoint d; // adds new coverpoint
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cross a, d; // crosses new coverpoint with inherited one
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endgroup :g1
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endclass
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endmodule
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