31 lines
636 B
Systemverilog
31 lines
636 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off COVERIGN */
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class myClass;
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covergroup embeddedCg;
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endgroup
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function new();
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embeddedCg = new();
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embeddedCg.sample();
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embeddedCg.get_coverage();
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endfunction
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endclass
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class secondClass;
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covergroup embeddedCg;
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endgroup
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function new();
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embeddedCg = new();
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embeddedCg.sample();
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embeddedCg.get_coverage();
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endfunction
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endclass
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