144 lines
4.0 KiB
Systemverilog
144 lines
4.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`define signal(name, width) wire [width-1:0] name;
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module t (
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`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py
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rand_a, rand_b, srand_a, srand_b
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);
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`include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py
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input rand_a;
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input rand_b;
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input srand_a;
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input srand_b;
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wire logic [63:0] rand_a;
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wire logic [63:0] rand_b;
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wire logic signed [63:0] srand_a;
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wire logic signed [63:0] srand_b;
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//////////////////////////////////////////////////////////////////////////
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// Interesting user code to cover
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//////////////////////////////////////////////////////////////////////////
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`signal(GRAY_SEL, 3);
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assign GRAY_SEL = rand_a[2:0] ^ 3'(GRAY_SEL[2:1]);
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`signal(GRAY_SHIFT, 3);
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assign GRAY_SHIFT = rand_a[2:0] ^ (GRAY_SHIFT >> 1);
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`signal(GRAY_REV_SEL, 3);
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assign GRAY_REV_SEL = rand_a[2:0] ^ {GRAY_REV_SEL[1:0], 1'b0};
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`signal(GRAY_REV_SHIFT, 3);
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assign GRAY_REV_SHIFT = rand_a[2:0] ^ (GRAY_REV_SHIFT << 1);
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//////////////////////////////////////////////////////////////////////////
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// Fill coverage
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//////////////////////////////////////////////////////////////////////////
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`signal(CONCAT_RHS, 2);
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assign CONCAT_RHS[0] = rand_a[0];
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assign CONCAT_RHS[1] = CONCAT_RHS[0];
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`signal(CONCAT_LHS, 2);
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assign CONCAT_LHS[0] = CONCAT_LHS[1];
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assign CONCAT_LHS[1] = rand_a[1];
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`signal(CONCAT_MID, 3);
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assign CONCAT_MID[0] = |CONCAT_MID[2:1];
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assign CONCAT_MID[2:1] = {rand_a[2], ~rand_a[2]};
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`signal(SEL, 3);
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assign SEL[0] = rand_a[4];
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assign SEL[1] = SEL[0];
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assign SEL[2] = SEL[1];
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`signal(EXTEND, 8);
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assign EXTEND[0] = rand_a[3];
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assign EXTEND[3:1] = 3'(EXTEND[0]);
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assign EXTEND[4] = EXTEND[1];
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assign EXTEND[6:5] = EXTEND[2:1];
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assign EXTEND[7] = EXTEND[3];
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`signal(NOT, 3);
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assign NOT = ~(rand_a[2:0] ^ 3'(NOT[2:1]));
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`signal(AND, 3);
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assign AND = rand_a[2:0] & 3'(AND[2:1]);
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`signal(OR, 3);
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assign OR = rand_a[2:0] | 3'(OR[2:1]);
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`signal(SHIFTR, 14);
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assign SHIFTR = {
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SHIFTR[6:5], // 13:12
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SHIFTR[7:6], // 11:10
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SHIFTR[5:4], // 9:8
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SHIFTR[3:0] >> 2, // 7:4
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rand_a[3:0] // 3:0
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};
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`signal(SHIFTR_VARIABLE, 2);
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assign SHIFTR_VARIABLE = rand_a[1:0] ^ ({1'b0, SHIFTR_VARIABLE[1]} >> rand_b[0]);
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`signal(SHIFTL, 14);
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assign SHIFTL = {
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SHIFTL[6:5], // 13:12
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SHIFTL[7:6], // 11:10
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SHIFTL[5:4], // 9:8
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SHIFTL[3:0] << 2, // 7:4
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rand_a[3:0] // 3:0
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};
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`signal(SHIFTL_VARIABLE, 2);
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assign SHIFTL_VARIABLE = rand_a[1:0] ^ ({SHIFTL_VARIABLE[0], 1'b0} << rand_b[0]);
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`signal(VAR_A, 2);
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wire logic [1:0] VAR_B;
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assign VAR_A = {rand_a[0], VAR_B[0]};
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assign VAR_B = (VAR_A >> 1) ^ 2'(VAR_B[1]);
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`signal(REPLICATE, 4);
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assign REPLICATE = rand_a[3:0] ^ ({2{REPLICATE[3:2]}} >> 2);
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`signal(PARTIAL, 4);
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assign PARTIAL[0] = rand_a[0];
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// PARTIAL[1] intentionally unconnected
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assign PARTIAL[3:2] = rand_a[3:2] ^ {PARTIAL[2], PARTIAL[0]};
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wire [2:0] array_0 [2];
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assign array_0[0] = rand_a[2:0];
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assign array_0[1] = array_0[0];
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`signal(ARRAY_0, 3);
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assign ARRAY_0 = array_0[1];
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wire [2:0] array_1 [1];
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assign array_1[0][0] = rand_a[0];
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assign array_1[0][1] = array_1[0][0];
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assign array_1[0][2] = array_1[0][1];
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`signal(ARRAY_1, 3);
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assign ARRAY_1 = array_1[0];
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wire [2:0] array_2a [2];
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wire [2:0] array_2b [2];
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assign array_2a[0][0] = rand_a[0];
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assign array_2a[0][1] = array_2b[1][0];
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assign array_2a[0][2] = array_2b[1][1];
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assign array_2a[1] = array_2a[0];
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assign array_2b = array_2a;
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`signal(ARRAY_2, 3);
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assign ARRAY_2 = array_2a[0];
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wire [2:0] array_3 [2];
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assign array_3[0] = rand_a[2:0] ^ array_3[1] >> 1;
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assign array_3[1] = array_3[0];
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`signal(ARRAY_3, 3);
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assign ARRAY_3 = array_3[0];
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endmodule
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