28 lines
635 B
Systemverilog
28 lines
635 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module mul (input [8:0] A, input [16:0] B, output [25:0] Y);
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assign Y = $signed(A) * $signed(B);
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endmodule
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module A;
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wire [26:0] C;
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wire [26:0] D;
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wire [8:0] E;
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// This yields a circular DFG with a fairly special form that used to trip
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// decomposition.
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mul mul (
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.A(9'd10),
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.B(17'h0cccd),
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.Y({ C[26], C[9:0], D[15:1] })
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);
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assign E = { C[8:0] };
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assign C[25:10] = {16{C[26]}};
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endmodule
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