17 lines
402 B
Systemverilog
17 lines
402 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`default_nettype none
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module t(
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output wire [9:0] o
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);
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assign o[1:0] = o[9:8];
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assign o[3:2] = {o[0], o[1]};
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assign o[7:4] = 4'(o[3:2]);
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assign o[9:8] = o[5:4];
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endmodule
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