17 lines
367 B
Systemverilog
17 lines
367 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire clk,
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output wire [31:0] o0
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);
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int file;
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assign o0 = $fgetc(file); // Impure
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endmodule
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