32 lines
626 B
Systemverilog
32 lines
626 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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task disable_fork_blk;
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disable t.init.fork_blk;
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endtask
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module t(/*AUTOARG*/);
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initial begin : init
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int x = 0;
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fork : fork_blk
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begin
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x = 1;
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disable_fork_blk();
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x = 2;
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end
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begin
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#1;
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x = 3;
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end
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join
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if (x != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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