20 lines
519 B
Systemverilog
20 lines
519 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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enum bit signed [3:0] {OK1 = -1} ok1_t; // As is signed, loss of 1 bits is ok per IEEE
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enum bit signed [3:0] {OK2 = 3} ok2_t;
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typedef enum [2:0] { VALUE_BAD1 = 8 } enum_t;
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enum bit [4:0] {BAD2[4] = 100} bad2;
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enum logic [3:0] {BAD3 = 5'bxxxxx} bad3;
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initial $stop;
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endmodule
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