47 lines
877 B
Systemverilog
47 lines
877 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef struct {int a;} s_t;
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typedef enum s_t { // BAD
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EN_ZERO
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} bad_t;
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typedef int int_t;
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enum int_t [1:0] { // BAD enum type
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INTRANGE_VAL
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} intrange_e;
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typedef bit [1:0][1:0] d2_t;
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enum d2_t { // BAD enum type
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TD2_VAL
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} td2_e;
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enum logic [1:0][1:0] { // BAD enum type
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D2_VAL
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} d2_e;
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typedef struct packed {int x;} str_t;
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enum str_t { // BAD enum type
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STR_VAL
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} str_e;
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typedef enum {ENUM_VAL} enum_t;
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enum enum_t { // BAD enum type
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ENUMT_VAL
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} enumt_val;
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typedef logic array2_t[1:0];
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enum array2_t { // BAD enum type
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ARRAY2_VAL
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} array2_e;
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initial $stop;
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endmodule
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