25 lines
475 B
Systemverilog
25 lines
475 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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event e;
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task trig_e();
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->> e;
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endtask
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endclass
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module top();
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event e;
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initial begin
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Cls c;
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c = new;
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c.trig_e();
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wait(e.triggered);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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