43 lines
786 B
Systemverilog
43 lines
786 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t;
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reg [1:0] a;
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wire [1:0] b = 1;
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initial begin
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#1 a = 0;
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force b = a;
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`checkh(a, 0);
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`checkh(b, 0);
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a = 1;
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#1;
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`checkh(a, 1);
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`checkh(b, 1);
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a = 2;
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#1;
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`checkh(a, 2);
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`checkh(b, 2);
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a = 3;
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#1;
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`checkh(a, 3);
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`checkh(b, 3);
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release b;
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`checkh(a, 3);
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`checkh(b, 1);
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#1 $finish;
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end
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endmodule
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