32 lines
776 B
Systemverilog
32 lines
776 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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reg [63:0] sum; // Checked not in objects
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reg [2:1] [4:3] array [5:6] [7:8];
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initial begin
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sum = 0;
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foreach (array[]) begin // NOP
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++sum;
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end
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`checkh(sum, 0);
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sum = 0;
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foreach (array[,,]) begin // NOP
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++sum;
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end
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`checkh(sum, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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