38 lines
751 B
Systemverilog
38 lines
751 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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Iface ifc();
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rvlab_tests uut (.ifc);
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always begin
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uut.test_idcode();
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end
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initial begin
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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interface Iface;
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logic tck;
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logic tdo;
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task tsk(output logic [31:0] data_o, input logic [31:0] data_i);
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@(posedge tck);
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data_o[$size(data_i)-1] <= tdo;
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endtask
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endinterface
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module rvlab_tests (
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Iface ifc);
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task test_idcode();
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bit [31:0] idcode_read;
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ifc.tsk(idcode_read, '0);
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endtask
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endmodule
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