61 lines
1.4 KiB
Systemverilog
61 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clock;
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initial begin
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clock = '0;
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forever begin
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clock = #5ns ~clock;
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end
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end
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task static has_fork_task(input [31:0] address);
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@(posedge clock);
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fork
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begin
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repeat($urandom_range(9)) @(posedge clock);
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end
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join
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endtask
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// Intentionally created a recursive task chain (that should be unreachable anyway):
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// call_task()
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// --> (unreachable) --> calls local_sub_task()
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// --> calls call_task()
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// --> ...
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// --> (reachable) --> calls has_fork_task() done.
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task static call_task(input [31:0] address);
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if (1) begin
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// Workaround1: Comment this out to pass the compile.
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has_fork_task(address);
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end
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else begin
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// Workaround2: Comment this out to pass the compile
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// Should be unreachable anyway.
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local_sub_task(.address(address));
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end
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endtask
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task static local_sub_task(input [31:0] address);
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logic [63:0] req;
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logic [39:0] resp;
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req = '0;
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call_task(.address(32'h0000_1234));
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resp = '0;
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endtask
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initial begin : main
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#100ns;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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