24 lines
832 B
Systemverilog
24 lines
832 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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class tb_cpu_seq_item;
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virtual function void uvm_report_error(string message);
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$display("%s", message);
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endfunction
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virtual function string get_type_name();
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return "GTN";
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endfunction
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virtual function bit do_compare( tb_cpu_seq_item rhs, int comparer);
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uvm_report_error($sformatf("this is of type %s, rhs is of type %s", this.get_type_name(), rhs.get_type_name()));
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uvm_report_error($sformatf("this is of type %s, rhs is of type %s", this.get_type_name, rhs.get_type_name));
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endfunction
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endclass
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endpackage
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module t;
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endmodule
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