35 lines
675 B
Systemverilog
35 lines
675 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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function int fi();
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return 10;
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endfunction
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static function int sfi();
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return 10;
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endfunction
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endclass
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module t;
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function int f1;
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return 20;
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endfunction
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initial begin
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Cls c;
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//
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f1(); // Bad - ignored result
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//
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c = new;
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c.fi(); // Bad - ignored result
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c.sfi(); // Bad - ignored result
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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