34 lines
605 B
Systemverilog
34 lines
605 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module GND(output G);
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assign G = 0;
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endmodule
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module CARRY2(
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output [1:0] CO,
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input CI,
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input [1:0] DI, S
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);
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assign CO[0] = S[0] ? CI : DI[0];
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assign CO[1] = S[1] ? CO[0] : DI[1];
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endmodule
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module A;
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wire const0;
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wire ci;
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GND GND (
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.G(const0)
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);
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CARRY2 CARRY2 (
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.CO(),
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.CI(ci),
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.DI({const0,const0}),
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.S({const0,const0})
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);
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endmodule
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