15 lines
342 B
Plaintext
15 lines
342 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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hier_block -module "Calculate"
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hier_block -module "Check"
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`ifdef WORKERS
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hier_workers -module "Calculate" -workers `WORKERS
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`endif
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