verilator/test_regress/t/t_inst_misarray2_bad.out

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%Error: t/t_inst_misarray2_bad.v:10:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6)
: ... note: In instance 't'
10 | .i_data(fft_oQ[6:0])
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to