verilator/test_regress/t/t_inst_misarray_bad.out

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%Error: t/t_inst_misarray_bad.v:17:23: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2023 7.6)
: ... note: In instance 't'
17 | .foo(foo));
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to