55 lines
1.1 KiB
Systemverilog
55 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface my_ifc ();
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logic sig;
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modport master ( output sig );
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modport slave ( input sig );
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endinterface
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package my_pkg;
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typedef virtual my_ifc my_vif;
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function void my_func;
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input my_vif in_vif;
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begin
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in_vif.sig = 1'b1;
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end
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endfunction
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endpackage
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module dut (input logic clk, my_ifc.slave sif[2]);
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generate
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genvar i;
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for (i=0; i<2; i++) begin
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always_ff @( posedge clk ) begin
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if (sif[i].sig == 1'b1) $display("Hello World %0d", i);
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end
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end
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endgenerate
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endmodule
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module t;
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import my_pkg::*;
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logic clk;
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my_ifc sif[2] ();
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dut DUT (.*);
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initial begin
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clk = 0;
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forever #(5) clk = ~clk;
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end
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initial begin
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repeat (4) @(posedge clk);
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my_func(sif[0]);
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my_func(sif[1]);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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